The present invention relates to a circuit for controlling redundancy in a semiconductor memory apparatus. More particularly, the present invention relates to a circuit for controlling redundancy in a semiconductor memory apparatus which is capable of increasing an area margin.
Generally, a semiconductor memory apparatus includes many memory cells. If any one of such memory cells is defective, then the entire semiconductor memory apparatus may operate in error. Recent developments in a semiconductor memory apparatus employs a redundancy control circuit which previously recognizes a defected cell through a test and then switches to a cell belonging to a redundancy circuit instead of the defected cell if an access to the defected cell is requested. The redundancy circuit refers to a set of redundant memory cells additionally provided in a memory cell array and which provides a substitute replacement cell for the defected cell.
Meanwhile, the semiconductor memory apparatus is mainly divided into a core circuit area and a peripheral circuit area. The core circuit area includes a plurality of memory banks, and each memory bank includes a plurality of memory cells for storing data. The peripheral circuit area includes auxiliary circuits to control the operation of the core circuit area and which performs a variety of functions such as the setting of an operational mode, power control, and timing control between a clock and data.
The redundancy circuit is provided in the memory bank of the core circuit area, and the operation of the redundancy circuit is determined in accordance to the cut state of a set of existing fuses.
A circuit to control the typical redundancy circuit includes a peripheral circuit redundancy control block 10 and a memory bank redundancy control block 20 as shown in FIG. 1.
The peripheral circuit redundancy control block 10 includes an address buffer unit 110, a command buffer unit 120, a first flip-flop unit 130, a second flip-flop unit 140, a global address generating unit 150, and a command converting unit 160.
The address buffer unit 110 buffers an external address add_ext<1:n> to output a buffering address add_buf<1:n>. The command buffer unit 120 buffers an external command cmd_ext to output a buffering command cmd_buf. The first flip-flop unit 130 latches the buffering address add_buf<1:n> under the control of a clock clk. The second flip-flop unit 140 latches the buffering command cmd_buf under the clock clk. The global address generating unit 150 receives a latch address add_lat<1:n> output from the first flip-flop unit 130, a first internal command cmd_int1 output from the second flip-flop unit 140, and a refresh signal rfsh to generate a global address add_glb<1:n>. The command converting unit 160 receives a bank address add_bnk<1:m> and receives the first internal command cmd_int1 to generate a second internal command cmd_int2.
The memory bank redundancy control block 20 includes a local address generating unit 210, a fuse set unit 220, a delay unit 230, a redundant decoding unit 240, and a main decoding unit 250.
The local address generating unit 210 generates a local address add_loc<1:n> from the global address add_glb<1:n> corresponding to the input of the second internal command cmd_int2. The fuse set unit 220 receives the local address add_loc<1:n> and compares the local address add_loc<1:n> with output signals of a plurality of existing fuse circuits to generate a repair determination signal rpa. The delay unit 230 delays the local address add_loc<1:n> by a predetermined time to output a delay local address add_locd<1:n>. The redundant decoding unit 240 decodes the delay local address add_locd<1:n> in accordance to the enable state of the repair determination signal rpa to activate any one redundancy word line RWL. The main decoding unit 250 decodes the delay local address add_locd<1:n> in accordance to the enable state of the repair determination signal rpa to activate any one main word line MWL.
The “n” and “m” representing each address bit number are positive integers. The “n” may be identical to or different from the “m”. In other words, the first flip-flop unit 130 includes n flip-flop circuits, and the buffering address add_buf<1:n> is latched in each flip-flop circuit by one bit.
The external command cmd_ext is input to indicate an active mode of the semiconductor memory apparatus, and the refresh signal rfsh is generated by decoding a refresh command.
The global address generating unit 150 generates the global address add_glb<1:n> from latch address add_lat<1:n> in accordance to the indication of the first internal command cmd_int1. In addition, the command converting unit 160 generates the second internal command cmd_int2 by converting the first internal command cmd_int1 and delivers the second internal command cmd_int2 to a memory bank indicated by the bank address add_bnk<1:m>.
Generally, since the semiconductor memory apparatus includes a plurality of memory banks, the plural memory bank redundancy control blocks 20 exist by the number of the memory banks. The second internal command cmd_int2 indicates the operation of any one of the local address generating units 210 provided in the plural memory bank redundancy control blocks 20. The local address generating units 210, which is selected by the second internal command cmd_int2, receives the global address add_glb<1:n> to generate the local address add_loc<1:n>.
The fuse set unit 220 includes n fuse circuits, and the n fuse circuits generate signals in accordance to the connection or disconnection of fuses that is set in a test step. If the local address add_loc<1:n> is input into the n fuse circuits of the fuse set unit 220 in an active mode, then the fuse set unit 220 compares an output signal of the fuse circuit with the local address add_loc<1:n> by one bit to generate the repair determination signal rpa. The repair determination signal rpa activates the redundant decoding unit 240 or the main decoding unit 250 in accordance to the potential level thereof. For example, if the potential of the repair determination signal rpa is a high level, the repair determination signal rpa activates the redundant decoding unit 240. If the potential of the repair determination signal rpa is a low level, the repair determination signal rpa activates the main decoding unit 250.
The delay unit 230 is provided to synchronize timing to input the local address add_loc<1:n> to the redundant decoding unit 240 and the main decoding unit 250, with timing to deliver the repair determination signal rpa to the redundant decoding unit 240 and the main decoding unit 250. Thereafter, the redundant decoding unit 240 activated by the repair determination signal rpa activates a predetermined redundancy word line RWL based on the local address add_loc<1:n>. Similarly, the main decoding unit 250 activated by the repair determination signal rpa activates a predetermined main word line MWL based on the local address add_loc<1:n>.
As described above, the typical semiconductor memory apparatus includes a redundancy control circuit to replace a defected memory cell with a redundancy cell.
However, in the redundancy control circuit of the typical semiconductor memory apparatus, the fuse set unit 220 is provided in the memory bank redundancy control block 20, so that the area margin of the fuse set unit 220 may be reduced.
Generally, fuse cutting must be performed using a laser in a fuse circuit after the fuse circuit is designed. Accordingly, a predetermined area margin must be ensured for the fuse cutting. Therefore, since the fuse set unit 220 must have a predetermined area, it is difficult to reduce the area of the fuse set unit 220.
In addition, since the fuse set unit 220 is installed in a memory bank having a relatively insufficient available area as compared with that of the peripheral circuit region, the high integration of the semiconductor memory apparatus cannot be fully realized.